Non-volatile memory devices can maintain stored data even after power to the devices is turned off, and have an advantage in that the data stored in the non-volatile memory devices may be electrically erasable or programmable. For those reasons, non-volatile memory devices have been widely used in various portable electronic appliances for storing data. Recently, non-volatile memory devices have been used in highly technical appliances, such as digital cameras, MP3 players, cellular phones, etc.
FIG. 1 is a cross sectional view illustrating a conventional non-volatile memory device.
Referring to FIG. 1, a conventional non-volatile memory device includes a control gate 20, a tunnel oxide layer 14 and a floating gate 16 interposed between the control gate 20 and the tunnel oxide layer 14. An oxide/nitride/oxide (ONO) layer 18 is positioned between the control gate 20 and the floating gate 16.
Electrons are injected into the floating gate 16 from a channel by a channel hot carrier and are injected into the channel from the floating gate 16 by a Fowler-Nordheim (F-N) tunneling current, thereby programming and erasing data in a cell of the non-volatile memory device. When electrons are injected into the floating gate 16, a potential energy of the floating gate 16 is changed; thus, a threshold voltage of a transistor is varied in accordance with the potential energy change. As a result, data are programmed into the cell of the non-volatile memory. When the F-N tunneling current flows across the tunnel oxide layer 14, the electrons in the floating gate 16 are extracted into the channel, thereby erasing the data in the cell of the non-volatile memory device.
A non-volatile memory device is operated at a time when a control gate voltage, which is a voltage applied to the control gate 20 from a power source, is applied to the floating gate 18 (hereinafter referred to as floating gate voltage). Accordingly, a ratio of the floating gate voltage with respect to the control gate voltage (hereinafter referred to as coupling ratio) has an effect on operation characteristics of the non-volatile memory device. A conventional coupling ratio is influenced by capacitance Cono of the ONO layer 18 and capacitance Ctun of the tunnel oxide layer 14, as indicated in the following equation (1).
                    γ        =                              C            ono                                              C              tun                        +                          C              ono                                                          (        1        )            
In the above equation (1), γ denotes the coupling ratio of a non-volatile memory device.
However, recent high integration degree in a non-volatile memory device has remarkably reduced a cell distance between cells adjacent to each other in the non-volatile memory device, so that parasitic capacitance between the floating gates in the neighboring cells is no longer negligible. For this reason, the coupling ratio is required to be accommodated in view of the parasitic capacitance (Cfg) between floating gates adjacent to each other. That is, the floating gate voltage is determined by an adjacent control gate voltage that is applied to a control gate for a neighboring word line adjacent to a predetermined cell, as well as by the control gate voltage for the predetermined cell in a non-volatile memory device. Accordingly, the floating gate voltage is determined by both the control gate voltage and the adjacent control gate voltage. For this reason, the floating gate voltage and the coupling ratio is modified as illustrated in the following equations (2) and (3).
                              V          fg                =                                                            C                ono                            ⁢                              V                cg                                      +                                          C                fg                            ⁢                              V                1                                      +                                          C                fg                            ⁢                              V                2                                                                        C              tuv                        +                          C              ono                        +                          2              ⁢                              C                fg                                                                        (        2        )                                          γ          fg                =                              C            fg                                              C              tun                        +                          C              ono                        +                          2              ⁢                              C                fg                                                                        (        3        )            
As a result, the coupling ratio is reduced due to the parasitic capacitance Cfg, and programming and erasing data in the predetermined cell is influenced by a word line adjacent to the predetermined cell. Furthermore, a threshold voltage is varied in accordance with a change of potential energy of a neighboring floating gate. Particularly, the above threshold voltage variation causes an operation failure, for example, a read/write error in a non-volatile memory device. The smaller the width and gap distance between the cells adjacent to each other are, the more frequently and seriously generated the operation failure is.
An exemplary method of reducing parasitic capacitance Cfg is disclosed in Korean Laid-Open Patent Publication No. 2002-088554. According to the above Korean patent publication, a recessed portion is formed on a device isolation layer through a dry etching process, and polysilicon is deposited into the recessed portion as a floating gate, so that the floating gate is formed in the recessed portion of the device isolation layer. Accordingly, the parasitic capacitance is minimized due to the recessed portion. However, the dry etching for the recessed portion can cause damage to a top surface of the floating gate and the device isolation layer, thereby reducing the reliability of the device.